Digital signal processors utilizing a microcomputer have been developed to perform a variety of tasks more efficiently than can generally be achieved utilizing a general purpose microprocessor. One standard division technique employed in such digital signal processors utilizes a radix 2 non-restoring divide algorithm. Such a known operation utilizes the sequence shown in TABLE I with the results of each processing step being repetitively stored in two accumulators to derive the final quotient and remainder.
In step 1 of TABLE I, an accumulator ACC1 which will eventually hold the remainder R, is initialized to 0. An accumulator ACC0 which will eventually hold the quotient Q, is loaded with the dividend d.
In step 2a, the remainder R is first tested to determine whether it is less than 0. Both the current R and Q values in accumulators ACC1 and ACC0 respectively, are then doubled and the most significant bit q of the dividend d currently stored in the accumulator ACC0, is added to the remainder R. Then depending upon the results of the test on the remainder R, the divisor D is either added to or subtracted from the current value of the remainder R to derive a new value for the remainder which is again stored in accumulator ACC1.
Under step 2b if the current value of the remainder R is negative, the quotient Q in the accumulator ACC0 remains the same. On the other hand if the value of R is greater than or equal to 0 the value of the quotient Q in the accumulator ACC0 is incremented by 1.
Once step 2 has been iterated n times (n being equal to the number of binary bits in the divident d), step 3 is performed once to restore the remainder R to a positive value if the current value in the accumulator ACC1 is negative.
As is well known, the values of R and Q in step 2a can be doubled by shifting them one position in the registers ACC1 and ACC0. It can be seen that it is necessary to test twice for the value of R during each iteration of the divide operation, in order to determine whether D should be added to or subtracted from R as detailed in step 2a, and then whether the quotient Q should remain the same or be incremented by 1 as detailed in step 2b. Hence using this standard technique, the remainder R must be tested twice during each step of the divide operation. Because it is necessary to test the value of R twice during each iteration of step 2, the number of instruction cycles is essentially double the number of binary bits in the dividend d. Step 3 is needed to restore the remainder to a positive value should the result in accumulator ACC1 be negative after step 2 is iterated n times.